The present invention relates to a semiconductor memory such as a dynamic random access memory (DRAM) and a method for manufacturing the semiconductor memory.
Today, semiconductor memories are employed in various electronic devices. A DRAM, which is a type of semiconductor memory, performs data write and data read by charging and discharging capacitor portions constituting memory cells. A data write is performed by raising the potential at a word line to turn on a transistor and charge a capacitor portion with a potential corresponding to the data from a selected bit line. A data read is performed by detecting the potential that is effected at the bit line by the charge stored at a capacitor portion when a transistor is turned on. Such DRAMs are widely employed as main storage devices in computers and OA apparatuses since their relatively simple structure achieves higher integration and larger capacity with ease.
Now, the structure of stacked (laminated) type memory cells in the prior art is described by referring to its manufacturing method presented in FIGS. 19-25. It is to be noted that in FIGS. 19-25, the figures (a)on the left-hand side each show the structure of the memory cell in a cross section intersecting the memory cell orthogonal to the direction of the wiring of word lines 104, whereas the figures (b) on the right-hand side each show the structure of the memory cell in a cross section intersecting the memory cell orthogonal to the direction of the wiring of bit lines 110.
First, as shown in FIGS. 19(a) and (b), a field oxide film 102 is formed at the surface of a semiconductor substrate (silicon substrate) 101. Then, as shown in FIGS. 20(a) and (b), a gate oxide film 103 is formed. Next, word lines 104 are formed by laminating polysilicon on the field oxide film 102 and performing patterning through photolithography/etching. After this, a CVD oxide film 105 is formed to cover the word lines 104, a thick oxide film is deposited through the LP-CVD method and etching is performed employing the RIE method to form side walls 106. Then, a diffusion layer 107 is formed through ion implantation.
Next, as illustrated in FIGS. 21(a) and (b), an oxide film 108 containing phosphorus and boron is deposited through the CVD method to constitute a first insulating film, and after implementing a flow through a heat treatment, a bit contact 109 is opened through photolithography/etching. Then, polysilicon is deposited and through photolithography/etching the bit lines 110 are formed, as illustrated in FIGS. 22(a) and (b). After this, as illustrated in FIGS. 23(a) and (b), an oxide film 111 containing phosphorus and boron is deposited through the CVD method to constitute a second insulating film, and a flow is implemented through a heat treatment.
Next, a thin capacitor insulating film for a capacitor that is to be formed during a subsequent step is formed, and after depositing a thick oxide film 112, which is required to assure a sufficient capacitor capacity through the LP-CVD method, a cell 113 is opened through photolithography/etching. Then, as illustrated in FIGS. 24(a) and (b), a storage electrode 114 to constitute the capacitor portion is formed, and then, as illustrated in FIGS. 25(a) and (b), the essential portion of the memory cell is completed by sequentially forming a capacitor insulating film 115 constituted of a thin nitride film and a cell plate electrode 116.
A heat treatment is implemented for purposes of activating impurities and the like when forming capacitor portions at a memory cells in this manner. During this step, if a stressed film is present on the oxide film 111 containing phosphorus and boron and having a degree of fluidity, the oxide film 111 will be caused to flow by the thermal stress. As a result, the bit lines 110, too, will be subject to the stress applied from their side surfaces, which raises a concern that the pattern, too, maybe caused to move together at locations where the wiring length is great. If the pattern of the bit lines 110 moves in this manner, the semiconductor memory will not operate correctly.
If, on the other hand, there is no stressed film present on the oxide film 111, the film thickness of the capacitor insulating film 115 cannot be reduced and, consequently, the required capacitor capacity for ensuring that the semiconductor memory operates correctly cannot be fully obtained. A stressed film must be provided on the oxide film 111 in order to reduce the film thickness of the capacitor insulating film 115.